电子工程专辑

Design Compiler: 加速IC设计收敛的新成员

缩短设计时间和提升设计性能是目前提升半导体公司市场竞争力的关键之一。在这里请大家进一步了解一下EDA厂商的动作，以半导体设计、验证和制造的软件及知识产权供应商Synopsys公司推出的Design Compiler为例。 缩短设计时间和提升设计性能是目前提升半导体 ...
Design-Reuse

Synopsys Custom Compiler Doubles New Customer Adoptions, Introduces New Release

Extraction Fusion and DRC Fusion technologies reduce the time it takes to achieve analog design closure. Extraction Fusion enables layout parasitics to be extracted from a partially completed layout.
电子工程专辑

Design Compiler NXT携手三星5/4纳米FinFET工艺技术，获好评无数！

新思科技（Synopsys）近日宣布其Design Compiler® NXT综合解决方案已获得三星Foundry认证，并用于三星的5/4纳米FinFET工艺技术。 Design ...
Design-Reuse

Synopsys Advances Custom Platform to Accelerate Robust Custom Design

MOUNTAIN VIEW, Calif. -- March 12, 2018 -- Synopsys, Inc. (Nasdaq: SNPS) today announced release of the latest versions of its circuit simulation and custom design products—HSPICE®, FineSim® SPICE, ...
New Electronics

Mentor’s LightSuite Photonic Compiler automated layout tool speeds integrated photonic ...

Mentor has announced the LightSuite Photonic Compiler – what it describes as the industry’s first integrated photonic automated layout system. This new tool enables companies designing integrated ...
Business Insider

Synopsys Custom Design Platform Delivers Breakthrough Analog Simulation and Fusion Technologies

FineSim SPICE 2018.09 delivers 3X faster runtime for analog circuits, adds RF analysis features Custom Compiler's Extraction Fusion with StarRC provides early parasitics for accurate pre-layout ...
EDN

EDA tools integration to address TSMC’s RF design flow migration

Three EDA toolmakers have joined hands to facilitate RF design flow migration from TSMC’s N16 process to its N6RF+ technology, which addresses the power, performance, and area (PPA) requirements of ...